This invention relates generally to computer systems and more particularly to video graphics processing.
Computers are known to include a central processing unit, system memory, audio processing circuitry, video graphics processing circuitry, and peripheral ports. The peripheral ports allow the central processing unit to transport data with peripheral devices such as monitors, external memory, printers, the Internet, keyboards, mouse, etc. In many computer architectures, an accelerated graphics port (AGP) chip set is included. The AGP chip set provides an interface between the central processing unit system memory, graphics circuitry, and peripheral ports. As such, the AGP chip set coordinates transport of data between such devices.
As the complexity of video graphics displays increases and as the size of displays increase, the amount of data transported from the video graphics circuit to a display is increasing. Currently, such display data is transported from the video graphics circuitry to the display in accordance with the digital flat panel (DFP) standard, which designates a 32-byte parallel signal for transporting the display data. However, with the increase in graphics complexity and display size, the DFP standards may be inadequate to support such data transports.
For example, if the display is a plasma display, which requires frame sequential color (FSC), the R component, G component, and B component are sent separately, thus requiring three times the typical 60 Hz refresh rate. In addition, the FSC bandwidth for the same display will be higher (e.g., 1.463 gigabytes per second in comparison to 1.064 gigabytes per second for a 1680-by-1210 UXGA display).
As is also known, the video graphics circuit for three-dimensional graphics receives vertex information of triangles of images via the AGP bus or the PCI bus. Upon receiving the vertex information, the video graphics circuit processes it to produce the display data. Accordingly, the amount of data the video graphic circuit receives via the AGP bus, or the PCI bus, is considerably less than the data transported by the video graphic circuit to the display. Thus, as the amount of display data increases due to the larger displays, displays using FSC, and/or more complex video graphics, a data bottleneck arises in transporting the display data from the video graphics circuit to the display.
Therefore, a need exists for a method and apparatus that extends the video graphics bus to the display, thereby reducing the data bottleneck to the display.